Technology has progressed from the days of single layer circuit boards, where individual active and passive components were interconnected on a surface by metal leads, wires and conductive traces. Today, as electronic systems require greater speed and complexity in smaller and smaller packages, printed circuit designers have been encouraged to develop printed circuit boards having greater circuit densities. Much of the early advances in printed circuit technology involved reductions in scale, such as by decreasing the line thicknesses for conductive traces, combining multiple functions on integrated circuit chips, and directly mounting integrated circuit chips through surface mounting processes. However, by restraining the printed circuit patterns to a single layer, exceedingly complex and space consuming wiring had to be implemented. Often, long runs of wire had to be used, whose internal resistance and capacitance introduced unacceptable electronc limitations.
The logical next step in the development of printed circuit technology involved the creation of double-sided circuit boards. These circuit boards typically comprise two circuit layers fabricated on each side of an insulating substrate. The two circuit layers are then connected by means of conductors passing through the insulating layer. While early double-sided boards used insulating layers made of a rigid resin or ceramic material, many printed circuit boards in use today employ flexible substrates, typically made of a polyester or polyimide material.
Double-sided circuits today are typically manufactured by forming electronic circuit patterns on opposing surfaces of the insulating layer. The patterns are formed by methods such as electroless and electrolytic plating of the opposing surfaces of the insulating layer with a conductive metal. A photoresist is layered over the conductive metal platings and exposed to a light or other radiation image of the desired circuit pattern. Finally, the unexposed photoresist is removed, and the portion of the conductive metal plating from which unexposed photoresist has been removed is etched away to relieve the desired conductive circuit patterns.
The two circuit layers on a double-sided circuit board are typically connected by the plated-through hole (PTH) method, which involves fabricating holes through the insulating layer and forming a layer of plated copper along the surface of the hole to electrically connect both layers. When used for double-sided printed circuit boards, the PTH process is exceptionally reliable. Although the thermal coefficient of expansion (TCE) for the copper and the insulating layer do not precisely match, the short barrel length (i.e., the length of the hole) obviates any concern about thermal mechanical stress.
While double-sided printed circuit board technology did significantly increase circuit density, further advancements in electronic systems required greater circuit density than could be obtained from double-sided printed circuit boards. Consequently, multilayer printed circuit boards began to be developed, having three or more interconnected conductive layers. However, unique problems exist in the fabrication of these multilayer printed circuit boards which are not easily resolved by many prior art fabrication techniques.
By a conductive layer, we mean a layer of conductive material disposed generally in a plane having a conductive pattern, and usually having a plurality of contact pads defined thereon. Such a layer is typically made of copper or another conductive metal, and is capable of transmitting electronic signals between components and other conductive layers electrically connected to the conductive layer. Of the contact pads on a conductive layer, some are designated interconnect pads, for interconnecting the conductive layer with other conductive layers. Conductive layers may be attached to one or both sides of a substrate, to form single or double sided circuit boards, respectively.
By a multi-layer electronic circuit, we mean a circuit having three or more of these conductive layers superposed with at least a portion of each adjacent set of layers overlapping, such that the layers are mechanically connected, and such that interconnect pads located on the various conductive layers are electrically connected, to transfer signals between the various layers. Adjacent layers are electrically insulated from one another, apart from the electrical connections between the interconnect pads located thereon.
The most common technique for fabricating multilayer circuits is simply an extension of the plated through hole method for manufacturing double-sided circuits. Conventional multilayers have been made by imaging, exposing, and etching various interlayers of circuitry and then bringing all layers together in alignment. The layers are then laminated together in plies using a suitable insulating adhesive. The multilayer product is then usually pressed, e.g. by means of a platen. Subsequent to pressing a cure of the adhesive is often required. Through holes are then drilled to form barrels which are plated to create electrical contact between layers.
The PTH process for multilayer printed circuit board construction is extraordinarily complex and for many applications is not a particularly reliable method of manufacture. One problem is that a typical PTH process will require holes be fabricated which run throughout the entire stack of layers. This requires that all of the layers be precisely aligned so that a reliable connection is made in each desired layer. The more layers that are involved, the more difficult is the alignment. Should the alignment in any layer be off by a small amount, there is a high probability that the through holes will not contact all desired electrical connection points and perhaps will contact undesired electrical contact points, thus creating undesired open and short circuits.
Another problem with the PTH process is that significant space may be wasted on layers which are not interconnected at a hole. For instance, in a 30 layer multilayer printed circuit board, a connection between the 2nd and the 28th layer would essentially render the area required for the hole useless in all of the intervening layers. In a complex circuit having hundreds or thousands of interconnections, this loss could become significant, and have a substantial effect on the circuit density of the board.
Another disadvantage of the PTH process is that the holes typically need to be fabricated all of the way through the entire multilayer circuit board. Although it is possible to create internal holes to partially connect certain layers, this requires a number of iterations of the standard fabrication process in order to construct these partial connections, which adds cost and complexity to the process.
The fabrication of the holes themselves is an additional problem associated with PTH processes. In double-sided circuit boards, the fabrication of the holes is often not problematic. Especially with flexible substrates, the holes may be fabricated by a mechanical mass piercing process. A standard punch press piercing process allows thousands of holes to be formed concurrently in a single step. However, for multilayer printed circuits, the holes must be formed by drilling, which is a much slower and more costly process. As opposed to the concurrent stamping process of a double-sided board, the drilling method must drill each hole individually, significantly increasing the time required for fabricating the holes.
The drilling process creates a number of additional problems, as drilling through many layers of metal, insulating layer, dielectric adhesive, and prepreg (interlayer bonding material) produces considerable contamination. The copper laminating adhesive and layer-bonding prepreg smear into the hole walls as the friction-heated drill moves in and then out. Burrs are also formed on the hole walls. The smear and burr problem is intensified with higher layer counts for several reasons. Each circuit layer contains two layers of adhesive and prepreg, so more layers means more smear-producing substance. Higher layer count also means greater drilling length, longer drill time and more frictional heat build up. All of this adds up to considerable smearing.
Due to this smearing and burring, additional steps must be implemented in a PTH process, because the smearing and burring prevents good plating from occurring and will result in unreliable copper barrel formation. Desmearing processes include chemical attack with oxidizers and high energy plasma bombardment. Etchback, the controlled removal of non-metallic material from the hole, is also essential in order to expose internal conductors. Desmearing and etchback must be effective and well controlled to produce reliable multilayer circuits by the PTH process. Too little desmearing produces a weak PTH barrel, and too much etchback causes a rough, irregular barrel which is prone to fracturing. As the number of layers increases, the barrels become longer, and the desmearing/etchback processes become more difficult.
Strong oxidizing chemicals such as sulfuric acid, chromic acid and permanganate are used to clean and etchback non-metallics. The desmearing/etchback methods are effective although difficult to control. They add cost and complexity to the multilayer process. Alternatively, combinations of vacuum plasma techniques and chemical processing may be used to desmear and etchback the multilayer drilled holes. Plasma desmearing/etchback involves bombarding the drilled laminate with a high energy gas plasma in a vacuum chamber. This plasma is produced by subjecting gases, such as oxygen and fluorocarbons, to a high voltage. The process takes from 5 to 30 or more minutes, but the method is very effective, especially for polyimide. The equipment is expensive, however.
The plating process results in further difficulties for the PTH process. To be prepared for plating the holes must be sensitized for the copper plating. Sensitizers, like palladium, are deposited onto the side walls of the holes, in a series of sequential steps. The sensitized holes are next exposed to electroless copper bath. In the bath, the copper salt or complex plates out where it contacts the sensitizer or copper metal surface.
The electroless process is relatively slow to allow an even deposition to take place. Plating bath agitation can supply sufficient copper ions to accommodate the plating process in most cases. However, the electroless process is typically too slow to provide the necessary thickness required for a reliable copper barrel. Electroless copper also usually does not have the right microstructure to produce the required strength and electrical performance for a PTH hole.
Instead, electrolytic plating is used to build up the additional desired barrel thickness. The higher speed electroplating process generates a greater demand for copper ion replenishment, however. Copper ions must be rapidly forced into tiny holes. Furthermore, electrical current must be conducted throughout the barrel surface. The electrolytic copper PTH process must overcome ion depletion and current density variation in order to be successful.
The dual dilemma of ion depletion and current density are intensified as barrel length is increased and hole size is reduced. Aspect ratio, the numerical relationship of hole length to width, is a key parameter for through-hole plating. The higher the aspect ratio, the more difficult it is to transport copper ions into the center of the barrel. Also, the higher the aspect ratio, the more divergent the current density. These natural phenomenon team up to make high aspect ratio very difficult without sacrificing product quality and process efficiency. As the current density is higher at the edge of the barrel than in the middle because of the electrical resistance of the thin copper barrel, copper ions will plate out of solution onto the nearest charged copper surface, resulting in thinner copper deposit towards the center of the barrel. As the number of layers increases, this disparity in copper thickness will be intensified, effectively limiting the maximum number of layers that may be connected. In order to increase the number of layers above this physical limitation, the diameter of the holes needs to be increased, which further intensifies the problem of wasted space on non-connected layers.
Due to all of these difficulties encountered in the PTH process for fabricating multilayer circuit boards, it can be seen that the cost of fabrication may be great. As the process is typically slow due to the number of steps involved and the time required for a number of the steps, it can be seen that the productivity of such processes is less than optimal. Furthermore, due to the many difficulties faced in the typical process, it has been common in the art to have a significant number of rejected boards, especially when dealing with large boards having hundreds or thousands of interconnections and more than twenty layers. Some reject rates on complex boards may approach 90%. Obviously, then, if multiple attempts must be made to produce a workable product, the overall cost becomes exceptionally high.
Even after a multilayer board is successfully produced by the PTH process, the multilayer board may be extremely sensitive to varying environmental conditions. Thermal mismatch between copper and dielectric insulation operates to significantly limit the ability of these boards to accommodate changes in temperature. Furthermore, increasing the copper barrel length by adding more layers only increases the stress placed upon the metal-organic structure. This is the primary reason that the layer count on both rigid and flexible multilayer circuits has been limited.
When a multilayer circuit is heated, both the copper and the dielectric adhesive composite and insulating layers expand, but at different rates. The expansion of the organic insulating material is typically significantly greater than the metal. For every degree of temperature rise, structural stress increases. A critical point is reached where the stress exceeds the strength limits of the copper. A number of events can occur to relieve the stresses. The copper barrel may elongate or even rupture, causing catastrophic failure. The copper area around the barrel on the surface of the circuit may bend upward or crack. The copper pads, or annular rings, can be damaged to the point of failure or just to the point of reduced reliability. The pad bending mode is so prevalent that circuitry specifications often allow a certain amount to occur without rejection.
A number of other failure mechanisms, all based on thermal mechanical stress, can also occur. The net result is that the high layer count multilayer circuits have reduced reliability from the temperature stressing viewpoint.
One attempt to overcome the problems associated with PTH processes is shown in U.S. Pat. No. 3,795,047, issued to Abolafia et al. This reference describes a multilayer electronic circuit having limited areas of metal powder and epoxy selectively applied at electrical connection points between two conductive layers. In order to construct a multilayer circuit having three double-sided circuit boards stacked together, epoxy resin must first be applied to selected exposed metal portions on the top surfaces of the bottom two circuit boards. A layer of metal particles are then sprinkled over the entire top surfaces of those boards, and the boards are then moderately heated to make the epoxy tacky. The metal particles stick only to the areas of tacky epoxy. Excess metal particles are then blown or brushed off of the top surfaces of the boards, so that only the particles clustered on the tacky epoxy on the connecting pads remain on the circuit boards. Next, thin layers of epoxy are placed across the surfaces opposing each of the surfaces with the selectively placed epoxy areas (the bottom surfaces of the top two circuit boards). All three boards are then carefully aligned, pressed together, heated and cooled. The cured epoxy holds the boards together, and the clusters of metal particles conduct between contact pads in the selective location.
Due to a number of problems associated with Abolafia et al., high density multilayer circuit boards may not be reliably produced with this method. The method of applying the metal particles at selective locations on the circuit board presents a number of problems. By "sprinkling" the metal particles, they are applied randomly throughout the top surfaces of the boards. Particles which are located on the same contact pad will most likely contact one another, and conduct in an x-y plane (the plane of the conductive layer). In Abolafia et al., this is not a problem due to the selective application of the metal particles. In addition, if the circuit board is very dense, and the area between contact pads is very small, some of the particles may bridge gaps between contact pads, and short circuit pads together. Finally, the random "sprinkling" process cannot be done in automated production lines and will probably leave some particles in areas which they are not desired, risking further short circuits. This is particularly problematic for boards having integrated circuit chips directly connected to the board by a surface mount technology (SMT) process. The metal particles may become lodged in between the chips and the board, or between adjacent chip connection points, furthering the risk of short circuits.
Another potential problem with Abolafia et al. is that the epoxy must be selectively applied to different points along the circuit board. For high density circuits with small line widths and spaces between lines, the registration of the epoxy may be difficult or even impossible to be performed reliably. This would further increase the probability of short circuits from the metal powder.
Finally, the process of Abolafia et al., while being significantly simpler than the PTH process, still requires a number of steps to adequately secure the boards together. The reference requires selective registration of adhesive, application of metal powder, removal of excess metal powder, additional registration of adhesive along the other surface, and finally, alignment, pressing and heating to create the full assembly.
Also related generally to the present invention are a number of references which disclose the use of anisotropic or z-axis conductive adhesives for mounting devices or replacing connectors on a circuit board. By a conductive adhesive, we mean an adhesive which may be used for both mechanical and electrical connection. These adhesives are typically comprised of some type of electroconductive particles disposed within an electrically insulating adhesive material, such that each particle is surrounded on all sides by the insulating adhesive.
For instance, the conductive adhesive disclosed in U.K. Patent Application No. 2,068,645 and French Patent Application No. 2,475,302, consists of a number of silver coated glass spheres disposed within a thermoplastic material. The conductive particles are sized such that one or two of them is sufficient to bridge the gap between opposed planar conductors.
Likewise, European Patent Application No. 265,212 entitled "Electroconductive Particles and Electroconductive Adhesive Containing Said Particles" discloses conductive particles which are fine polymer particles with a thin metal layer disposed on their surfaces. The adhesive in which the particles are disposed throughout is preferably coated on with a thickness which is preferably about 1 to 3 times the average particle diameter of the conductive particles.
The above references are similar in the fact that the conductive particles are non-deformable. This results in connections being formed and maintained by the pressure exerted by the adhesive in holding the conductive layers together. Connections formed with this pressure-acting method are, in general, only moderately reliable, and may be prone to failure, especially during thermal cycling.
European Patent Application No. 147,856 entitled "Electrically Conductive Adhesive Sheet, Circuit Board and Electrical Connection Structure Using the Same", discloses an electrically conductive adhesive sheet having a number of electrically conductive metal particles disposed within an insulating adhesive. The metal particles are typically deformable bodies such as solder particles. During a heat and pressure applying step, these particles are "squashed" between the conductive layers, and reflowed to form fused connections which are more reliable than the connections formed only from providing pressure.
None of the above references disclose conductive adhesives which may be used to construct multilayer circuit boards. The conductive adhesives are instead used to provide interfaces between circuit boards and connectors or surface mounted components, typically after the circuit boards have been manufactured. They are typically substitutes for soldering, wire bonding, or for connectors.
As such, the conductive adhesives are not designed to handle a number of difficulties which exist in creating reliable and complicated multilayer circuit boards. Most importantly, these conductive adhesives are unable to withstand the temperatures required for component assembly. This is because these adhesives are used after a circuit board has been completed. Much of the high temperature soldering processes have already been applied prior to the application of the adhesives. Therefore, they are not developed for the purpose of having heat resistant properties.
European Patent Application No. 346,525 entitled "Multilayer Electronic Circuit and Method of Manufacture" whose applicant is the same as the applicant of the present invention, discloses a multilayer electronic circuit comprising three or more electronic circuit layers connected by an interconnector layer which contains fusible solder particles. The quantity of the particles is selected to be sufficiently dispersed to prevent electrical conduction along the x and y axes and sufficiently concentrate and of a size to enable conduction along z axis.
However, the conductive adhesives above do not take into account for thermal expansion, as the applications for which they are used do not typically involve high or low temperatures. Due to a mismatch in thermal coefficients of expansion (TCE) between the adhesives and the insulating substrates or films which are being connected, the connections created by these conductive adhesives may inadvertently open during thermal cycling. Finally, the adhesives themselves may not be temperature resistant, and may soften or lose their bond ply under excessive temperatures.
Consequentially, a need exists in the art for a multilayer circuit board having a plurality of conductive layers, which has reliable interconnections between layers that are capable of withstanding thermal cycling. Furthermore, a need exists for a method of making such multilayer circuits which is less complex than the prior PTH processes and which produces reliable interconnections between many conductive layers.